Browse Source

Added a simple LED blinking firmware

Based on the RT-STM32F072-DISCOVERY demo from ChibiOS/demos/STM32.  The
board definition was made with the Eclipse plugin, and is based on the
ST_STM32F072B_DISCOVERY board definition from ChibiOS/os/hal/boards.
Clara Hobbs 4 years ago
parent
commit
e1fe690dbc
10 changed files with 3138 additions and 0 deletions
  1. 3
    0
      .gitignore
  2. 212
    0
      Makefile
  3. 107
    0
      boards/PD_BUDDY/board.c
  4. 916
    0
      boards/PD_BUDDY/board.h
  5. 5
    0
      boards/PD_BUDDY/board.mk
  6. 703
    0
      boards/PD_BUDDY/cfg/board.chcfg
  7. 499
    0
      chconf.h
  8. 381
    0
      halconf.h
  9. 247
    0
      mcuconf.h
  10. 65
    0
      src/main.c

+ 3
- 0
.gitignore View File

@@ -32,3 +32,6 @@
32 32
 # Debug files
33 33
 *.dSYM/
34 34
 
35
+# ChibiOS build
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+.dep/
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+build/

+ 212
- 0
Makefile View File

@@ -0,0 +1,212 @@
1
+##############################################################################
2
+# Build global options
3
+# NOTE: Can be overridden externally.
4
+#
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+
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+# Compiler options here.
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+ifeq ($(USE_OPT),)
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+  USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
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+endif
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+
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+# C specific options here (added to USE_OPT).
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+ifeq ($(USE_COPT),)
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+  USE_COPT = 
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+endif
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+
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+# C++ specific options here (added to USE_OPT).
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+ifeq ($(USE_CPPOPT),)
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+  USE_CPPOPT = -fno-rtti
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+endif
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+
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+# Enable this if you want the linker to remove unused code and data
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+ifeq ($(USE_LINK_GC),)
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+  USE_LINK_GC = yes
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+endif
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+
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+# Linker extra options here.
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+ifeq ($(USE_LDOPT),)
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+  USE_LDOPT = 
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+endif
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+
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+# Enable this if you want link time optimizations (LTO)
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+ifeq ($(USE_LTO),)
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+  USE_LTO = yes
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+endif
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+
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+# If enabled, this option allows to compile the application in THUMB mode.
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+ifeq ($(USE_THUMB),)
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+  USE_THUMB = yes
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+endif
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+
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+# Enable this if you want to see the full log while compiling.
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+ifeq ($(USE_VERBOSE_COMPILE),)
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+  USE_VERBOSE_COMPILE = no
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+endif
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+
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+# If enabled, this option makes the build process faster by not compiling
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+# modules not used in the current configuration.
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+ifeq ($(USE_SMART_BUILD),)
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+  USE_SMART_BUILD = yes
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+endif
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+
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+#
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+# Build global options
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+##############################################################################
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+
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+##############################################################################
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+# Architecture or project specific options
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+#
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+
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+# Stack size to be allocated to the Cortex-M process stack. This stack is
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+# the stack used by the main() thread.
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+ifeq ($(USE_PROCESS_STACKSIZE),)
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+  USE_PROCESS_STACKSIZE = 0x200
64
+endif
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+
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+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
67
+# stack is used for processing interrupts and exceptions.
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+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
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+  USE_EXCEPTIONS_STACKSIZE = 0x400
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+endif
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+
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+#
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+# Architecture or project specific options
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+##############################################################################
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+
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+##############################################################################
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+# Project, sources and paths
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+#
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+
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+# Define project name here
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+PROJECT = pd-buddy-firmware
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+
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+# Imported source files and paths
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+CHIBIOS = ChibiOS
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+# Startup files.
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+include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
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+# HAL-OSAL files (optional).
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+include $(CHIBIOS)/os/hal/hal.mk
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+include $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/platform.mk
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+include $(CHIBIOS)/../boards/PD_BUDDY/board.mk
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+include $(CHIBIOS)/os/hal/osal/rt/osal.mk
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+# RTOS files (optional).
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+include $(CHIBIOS)/os/rt/rt.mk
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+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
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+# Other files (optional).
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+include $(CHIBIOS)/test/rt/test.mk
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+
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+# Define linker script file here
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+LDSCRIPT= $(STARTUPLD)/STM32F072xB.ld
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+
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+# C sources that can be compiled in ARM or THUMB mode depending on the global
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+# setting.
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+CSRC = $(STARTUPSRC) \
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+       $(KERNSRC) \
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+       $(PORTSRC) \
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+       $(OSALSRC) \
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+       $(HALSRC) \
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+       $(PLATFORMSRC) \
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+       $(BOARDSRC) \
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+       $(TESTSRC) \
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+       $(wildcard src/*.c)
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+
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+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
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+# setting.
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+CPPSRC =
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+
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+# C sources to be compiled in ARM mode regardless of the global setting.
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+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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+#       option that results in lower performance and larger code size.
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+ACSRC =
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+
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+# C++ sources to be compiled in ARM mode regardless of the global setting.
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+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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+#       option that results in lower performance and larger code size.
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+ACPPSRC =
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+
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+# C sources to be compiled in THUMB mode regardless of the global setting.
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+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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+#       option that results in lower performance and larger code size.
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+TCSRC =
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+
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+# C sources to be compiled in THUMB mode regardless of the global setting.
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+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
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+#       option that results in lower performance and larger code size.
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+TCPPSRC =
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+
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+# List ASM source files here
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+ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
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+
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+INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
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+         $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \
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+         $(CHIBIOS)/os/various \
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+	 config
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+
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+#
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+# Project, sources and paths
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+##############################################################################
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+
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+##############################################################################
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+# Compiler settings
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+#
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+
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+MCU  = cortex-m0
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+
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+#TRGT = arm-elf-
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+TRGT = arm-none-eabi-
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+CC   = $(TRGT)gcc
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+CPPC = $(TRGT)g++
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+# Enable loading with g++ only if you need C++ runtime support.
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+# NOTE: You can use C++ even without C++ support if you are careful. C++
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+#       runtime support makes code size explode.
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+LD   = $(TRGT)gcc
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+#LD   = $(TRGT)g++
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+CP   = $(TRGT)objcopy
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+AS   = $(TRGT)gcc -x assembler-with-cpp
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+AR   = $(TRGT)ar
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+OD   = $(TRGT)objdump
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+SZ   = $(TRGT)size
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+HEX  = $(CP) -O ihex
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+BIN  = $(CP) -O binary
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+
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+# ARM-specific options here
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+AOPT =
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+
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+# THUMB-specific options here
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+TOPT = -mthumb -DTHUMB
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+
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+# Define C warning options here
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+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
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+
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+# Define C++ warning options here
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+CPPWARN = -Wall -Wextra -Wundef
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+
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+#
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+# Compiler settings
186
+##############################################################################
187
+
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+##############################################################################
189
+# Start of user section
190
+#
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+
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+# List all user C define here, like -D_DEBUG=1
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+UDEFS =
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+
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+# Define ASM defines here
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+UADEFS =
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+
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+# List all user directories here
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+UINCDIR =
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+
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+# List the user directory to look for the libraries here
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+ULIBDIR =
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+
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+# List all user libraries here
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+ULIBS =
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+
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+#
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+# End of user defines
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+##############################################################################
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+
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+RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
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+include $(RULESPATH)/rules.mk

+ 107
- 0
boards/PD_BUDDY/board.c View File

@@ -0,0 +1,107 @@
1
+/*
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+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
+
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+    Licensed under the Apache License, Version 2.0 (the "License");
5
+    you may not use this file except in compliance with the License.
6
+    You may obtain a copy of the License at
7
+
8
+        http://www.apache.org/licenses/LICENSE-2.0
9
+
10
+    Unless required by applicable law or agreed to in writing, software
11
+    distributed under the License is distributed on an "AS IS" BASIS,
12
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+    See the License for the specific language governing permissions and
14
+    limitations under the License.
15
+*/
16
+
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+/*
18
+ * This file has been automatically generated using ChibiStudio board
19
+ * generator plugin. Do not edit manually.
20
+ */
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+
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+#include "hal.h"
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+
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+#if HAL_USE_PAL || defined(__DOXYGEN__)
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+/**
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+ * @brief   PAL setup.
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+ * @details Digital I/O ports static configuration as defined in @p board.h.
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+ *          This variable is used by the HAL when initializing the PAL driver.
29
+ */
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+const PALConfig pal_default_config = {
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+#if STM32_HAS_GPIOA
32
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
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+#endif
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+#if STM32_HAS_GPIOB
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+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
38
+#endif
39
+#if STM32_HAS_GPIOC
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+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
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+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
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+#endif
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+#if STM32_HAS_GPIOD
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+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
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+#endif
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+#if STM32_HAS_GPIOE
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+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
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+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
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+#endif
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+#if STM32_HAS_GPIOF
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+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
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+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
54
+#endif
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+#if STM32_HAS_GPIOG
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+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
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+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
58
+#endif
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+#if STM32_HAS_GPIOH
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+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
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+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
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+#endif
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+#if STM32_HAS_GPIOI
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+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
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+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
66
+#endif
67
+};
68
+#endif
69
+
70
+/**
71
+ * @brief   Early initialization code.
72
+ * @details This initialization must be performed just after stack setup
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+ *          and before any other initialization.
74
+ */
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+void __early_init(void) {
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+
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+  stm32_clock_init();
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+}
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+
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+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
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+/**
82
+ * @brief   MMC_SPI card detection.
83
+ */
84
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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+
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+  (void)mmcp;
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+  /* TODO: Fill the implementation.*/
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+  return true;
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+}
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+
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+/**
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+ * @brief   MMC_SPI card write protection detection.
93
+ */
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+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
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+
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+  (void)mmcp;
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+  /* TODO: Fill the implementation.*/
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+  return false;
99
+}
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+#endif
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+
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+/**
103
+ * @brief   Board-specific initialization code.
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+ * @todo    Add your board-specific code, if any.
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+ */
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+void boardInit(void) {
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+}

+ 916
- 0
boards/PD_BUDDY/board.h View File

@@ -0,0 +1,916 @@
1
+/*
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+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
3
+
4
+    Licensed under the Apache License, Version 2.0 (the "License");
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+    you may not use this file except in compliance with the License.
6
+    You may obtain a copy of the License at
7
+
8
+        http://www.apache.org/licenses/LICENSE-2.0
9
+
10
+    Unless required by applicable law or agreed to in writing, software
11
+    distributed under the License is distributed on an "AS IS" BASIS,
12
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+    See the License for the specific language governing permissions and
14
+    limitations under the License.
15
+*/
16
+
17
+/*
18
+ * This file has been automatically generated using ChibiStudio board
19
+ * generator plugin. Do not edit manually.
20
+ */
21
+
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+#ifndef BOARD_H
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+#define BOARD_H
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+
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+/*
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+ * Setup for PD Buddy board.
27
+ */
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+
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+/*
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+ * Board identifier.
31
+ */
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+#define BOARD_PD_BUDDY
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+#define BOARD_NAME                  "PD Buddy"
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+
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+/*
36
+ * Board oscillators-related settings.
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+ * NOTE: LSE not fitted.
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+ * NOTE: HSE not fitted.
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+ */
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+#if !defined(STM32_LSECLK)
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+#define STM32_LSECLK                0U
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+#endif
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+
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+#define STM32_LSEDRV                (3U << 3U)
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+
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+#if !defined(STM32_HSECLK)
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+#define STM32_HSECLK                0U
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+#endif
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+
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+#define STM32_HSE_BYPASS
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+
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+/*
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+ * MCU type as defined in the ST header.
54
+ */
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+#define STM32F072xB
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+
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+/*
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+ * IO pins assignments.
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+ */
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+#define GPIOA_PIN0                  0U
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+#define GPIOA_PIN1                  1U
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+#define GPIOA_PIN2                  2U
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+#define GPIOA_PIN3                  3U
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+#define GPIOA_PIN4                  4U
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+#define GPIOA_PIN5                  5U
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+#define GPIOA_PIN6                  6U
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+#define GPIOA_PIN7                  7U
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+#define GPIOA_PIN8                  8U
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+#define GPIOA_PIN9                  9U
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+#define GPIOA_PIN10                 10U
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+#define GPIOA_USB_DM                11U
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+#define GPIOA_USB_DP                12U
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+#define GPIOA_SWDIO                 13U
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+#define GPIOA_SWCLK                 14U
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+#define GPIOA_LED                   15U
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+
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+#define GPIOB_PIN0                  0U
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+#define GPIOB_PIN1                  1U
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+#define GPIOB_PIN2                  2U
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+#define GPIOB_BUTTON                3U
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+#define GPIOB_PIN4                  4U
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+#define GPIOB_PIN5                  5U
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+#define GPIOB_PIN6                  6U
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+#define GPIOB_PIN7                  7U
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+#define GPIOB_OUT_CTRL              8U
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+#define GPIOB_PIN9                  9U
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+#define GPIOB_SCL                   10U
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+#define GPIOB_SDA                   11U
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+#define GPIOB_INT_N                 12U
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+#define GPIOB_PIN13                 13U
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+#define GPIOB_PIN14                 14U
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+#define GPIOB_PIN15                 15U
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+
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+#define GPIOC_PIN0                  0U
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+#define GPIOC_PIN1                  1U
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+#define GPIOC_PIN2                  2U
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+#define GPIOC_PIN3                  3U
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+#define GPIOC_PIN4                  4U
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+#define GPIOC_PIN5                  5U
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+#define GPIOC_PIN6                  6U
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+#define GPIOC_PIN7                  7U
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+#define GPIOC_PIN8                  8U
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+#define GPIOC_PIN9                  9U
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+#define GPIOC_PIN10                 10U
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+#define GPIOC_PIN11                 11U
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+#define GPIOC_PIN12                 12U
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+#define GPIOC_PIN13                 13U
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+#define GPIOC_PIN14                 14U
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+#define GPIOC_PIN15                 15U
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+
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+#define GPIOD_PIN0                  0U
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+#define GPIOD_PIN1                  1U
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+#define GPIOD_PIN2                  2U
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+#define GPIOD_PIN3                  3U
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+#define GPIOD_PIN4                  4U
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+#define GPIOD_PIN5                  5U
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+#define GPIOD_PIN6                  6U
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+#define GPIOD_PIN7                  7U
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+#define GPIOD_PIN8                  8U
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+#define GPIOD_PIN9                  9U
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+#define GPIOD_PIN10                 10U
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+#define GPIOD_PIN11                 11U
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+#define GPIOD_PIN12                 12U
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+#define GPIOD_PIN13                 13U
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+#define GPIOD_PIN14                 14U
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+#define GPIOD_PIN15                 15U
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+
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+#define GPIOE_PIN0                  0U
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+#define GPIOE_PIN1                  1U
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+#define GPIOE_PIN2                  2U
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+#define GPIOE_PIN3                  3U
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+#define GPIOE_PIN4                  4U
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+#define GPIOE_PIN5                  5U
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+#define GPIOE_PIN6                  6U
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+#define GPIOE_PIN7                  7U
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+#define GPIOE_PIN8                  8U
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+#define GPIOE_PIN9                  9U
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+#define GPIOE_PIN10                 10U
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+#define GPIOE_PIN11                 11U
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+#define GPIOE_PIN12                 12U
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+#define GPIOE_PIN13                 13U
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+#define GPIOE_PIN14                 14U
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+#define GPIOE_PIN15                 15U
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+
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+#define GPIOF_PIN0                  0U
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+#define GPIOF_PIN1                  1U
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+#define GPIOF_PIN2                  2U
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+#define GPIOF_PIN3                  3U
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+#define GPIOF_PIN4                  4U
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+#define GPIOF_PIN5                  5U
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+#define GPIOF_PIN6                  6U
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+#define GPIOF_PIN7                  7U
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+#define GPIOF_PIN8                  8U
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+#define GPIOF_PIN9                  9U
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+#define GPIOF_PIN10                 10U
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+#define GPIOF_PIN11                 11U
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+#define GPIOF_PIN12                 12U
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+#define GPIOF_PIN13                 13U
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+#define GPIOF_PIN14                 14U
160
+#define GPIOF_PIN15                 15U
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+
162
+/*
163
+ * IO lines assignments.
164
+ */
165
+#define LINE_USB_DM                 PAL_LINE(GPIOA, 11U)
166
+#define LINE_USB_DP                 PAL_LINE(GPIOA, 12U)
167
+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
168
+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)
169
+#define LINE_LED                    PAL_LINE(GPIOA, 15U)
170
+
171
+#define LINE_BUTTON                 PAL_LINE(GPIOB, 3U)
172
+#define LINE_OUT_CTRL               PAL_LINE(GPIOB, 8U)
173
+#define LINE_SCL                    PAL_LINE(GPIOB, 10U)
174
+#define LINE_SDA                    PAL_LINE(GPIOB, 11U)
175
+#define LINE_INT_N                  PAL_LINE(GPIOB, 12U)
176
+
177
+
178
+
179
+
180
+
181
+/*
182
+ * I/O ports initial setup, this configuration is established soon after reset
183
+ * in the initialization code.
184
+ * Please refer to the STM32 Reference Manual for details.
185
+ */
186
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
187
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
188
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
189
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
190
+#define PIN_ODR_LOW(n)              (0U << (n))
191
+#define PIN_ODR_HIGH(n)             (1U << (n))
192
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
193
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
194
+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
195
+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
196
+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
197
+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
198
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
199
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
200
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
201
+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))
202
+
203
+/*
204
+ * GPIOA setup:
205
+ *
206
+ * PA0  - PIN0                      (input pullup).
207
+ * PA1  - PIN1                      (input pullup).
208
+ * PA2  - PIN2                      (input pullup).
209
+ * PA3  - PIN3                      (input pullup).
210
+ * PA4  - PIN4                      (input pullup).
211
+ * PA5  - PIN5                      (input pullup).
212
+ * PA6  - PIN6                      (input pullup).
213
+ * PA7  - PIN7                      (input pullup).
214
+ * PA8  - PIN8                      (input pullup).
215
+ * PA9  - PIN9                      (input pullup).
216
+ * PA10 - PIN10                     (input pullup).
217
+ * PA11 - USB_DM                    (input floating).
218
+ * PA12 - USB_DP                    (input floating).
219
+ * PA13 - SWDIO                     (alternate 0).
220
+ * PA14 - SWCLK                     (alternate 0).
221
+ * PA15 - LED                       (output pushpull maximum).
222
+ */
223
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |           \
224
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
225
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
226
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
227
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
228
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
229
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
230
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
231
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
232
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
233
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
234
+                                     PIN_MODE_INPUT(GPIOA_USB_DM) |         \
235
+                                     PIN_MODE_INPUT(GPIOA_USB_DP) |         \
236
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
237
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
238
+                                     PIN_MODE_OUTPUT(GPIOA_LED))
239
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |       \
240
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
241
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
242
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
243
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
244
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
245
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
246
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
247
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
248
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
249
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
250
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) |     \
251
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) |     \
252
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
253
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
254
+                                     PIN_OTYPE_PUSHPULL(GPIOA_LED))
255
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOA_PIN0) |       \
256
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN1) |       \
257
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN2) |       \
258
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN3) |       \
259
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN4) |       \
260
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN5) |       \
261
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN6) |       \
262
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN7) |       \
263
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN8) |       \
264
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN9) |       \
265
+                                     PIN_OSPEED_VERYLOW(GPIOA_PIN10) |      \
266
+                                     PIN_OSPEED_VERYLOW(GPIOA_USB_DM) |     \
267
+                                     PIN_OSPEED_VERYLOW(GPIOA_USB_DP) |     \
268
+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \
269
+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \
270
+                                     PIN_OSPEED_HIGH(GPIOA_LED))
271
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_PIN0) |         \
272
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
273
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
274
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
275
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
276
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
277
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
278
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
279
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
280
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
281
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
282
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DM) |     \
283
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_DP) |     \
284
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDIO) |        \
285
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
286
+                                     PIN_PUPDR_FLOATING(GPIOA_LED))
287
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |             \
288
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
289
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
290
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
291
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
292
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
293
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
294
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
295
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
296
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
297
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
298
+                                     PIN_ODR_HIGH(GPIOA_USB_DM) |           \
299
+                                     PIN_ODR_HIGH(GPIOA_USB_DP) |           \
300
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
301
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
302
+                                     PIN_ODR_LOW(GPIOA_LED))
303
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |          \
304
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0U) |          \
305
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0U) |          \
306
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0U) |          \
307
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |          \
308
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0U) |          \
309
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0U) |          \
310
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0U))
311
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0U) |          \
312
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0U) |          \
313
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0U) |         \
314
+                                     PIN_AFIO_AF(GPIOA_USB_DM, 0U) |        \
315
+                                     PIN_AFIO_AF(GPIOA_USB_DP, 0U) |        \
316
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |         \
317
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |         \
318
+                                     PIN_AFIO_AF(GPIOA_LED, 0U))
319
+
320
+/*
321
+ * GPIOB setup:
322
+ *
323
+ * PB0  - PIN0                      (input pullup).
324
+ * PB1  - PIN1                      (input pullup).
325
+ * PB2  - PIN2                      (input pullup).
326
+ * PB3  - BUTTON                    (input floating).
327
+ * PB4  - PIN4                      (input pullup).
328
+ * PB5  - PIN5                      (input pullup).
329
+ * PB6  - PIN6                      (input pullup).
330
+ * PB7  - PIN7                      (input pullup).
331
+ * PB8  - OUT_CTRL                  (output pushpull minimum).
332
+ * PB9  - PIN9                      (input pullup).
333
+ * PB10 - SCL                       (alternate 1).
334
+ * PB11 - SDA                       (alternate 1).
335
+ * PB12 - INT_N                     (input floating).
336
+ * PB13 - PIN13                     (input pullup).
337
+ * PB14 - PIN14                     (input pullup).
338
+ * PB15 - PIN15                     (input pullup).
339
+ */
340
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
341
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
342
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
343
+                                     PIN_MODE_INPUT(GPIOB_BUTTON) |         \
344
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
345
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
346
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
347
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
348
+                                     PIN_MODE_OUTPUT(GPIOB_OUT_CTRL) |      \
349
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
350
+                                     PIN_MODE_ALTERNATE(GPIOB_SCL) |        \
351
+                                     PIN_MODE_ALTERNATE(GPIOB_SDA) |        \
352
+                                     PIN_MODE_INPUT(GPIOB_INT_N) |          \
353
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
354
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
355
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
356
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
357
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
358
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
359
+                                     PIN_OTYPE_PUSHPULL(GPIOB_BUTTON) |     \
360
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
361
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
362
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
363
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
364
+                                     PIN_OTYPE_PUSHPULL(GPIOB_OUT_CTRL) |   \
365
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
366
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SCL) |       \
367
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_SDA) |       \
368
+                                     PIN_OTYPE_PUSHPULL(GPIOB_INT_N) |      \
369
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
370
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
371
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
372
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOB_PIN0) |       \
373
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN1) |       \
374
+                                     PIN_OSPEED_HIGH(GPIOB_PIN2) |          \
375
+                                     PIN_OSPEED_VERYLOW(GPIOB_BUTTON) |     \
376
+                                     PIN_OSPEED_HIGH(GPIOB_PIN4) |          \
377
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN5) |       \
378
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN6) |       \
379
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN7) |       \
380
+                                     PIN_OSPEED_VERYLOW(GPIOB_OUT_CTRL) |   \
381
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN9) |       \
382
+                                     PIN_OSPEED_HIGH(GPIOB_SCL) |           \
383
+                                     PIN_OSPEED_HIGH(GPIOB_SDA) |           \
384
+                                     PIN_OSPEED_LOW(GPIOB_INT_N) |          \
385
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN13) |      \
386
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN14) |      \
387
+                                     PIN_OSPEED_VERYLOW(GPIOB_PIN15))
388
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
389
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
390
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
391
+                                     PIN_PUPDR_FLOATING(GPIOB_BUTTON) |     \
392
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
393
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
394
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
395
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
396
+                                     PIN_PUPDR_FLOATING(GPIOB_OUT_CTRL) |   \
397
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
398
+                                     PIN_PUPDR_FLOATING(GPIOB_SCL) |        \
399
+                                     PIN_PUPDR_FLOATING(GPIOB_SDA) |        \
400
+                                     PIN_PUPDR_FLOATING(GPIOB_INT_N) |      \
401
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
402
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
403
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
404
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
405
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
406
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
407
+                                     PIN_ODR_HIGH(GPIOB_BUTTON) |           \
408
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
409
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
410
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
411
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
412
+                                     PIN_ODR_LOW(GPIOB_OUT_CTRL) |          \
413
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
414
+                                     PIN_ODR_HIGH(GPIOB_SCL) |              \
415
+                                     PIN_ODR_HIGH(GPIOB_SDA) |              \
416
+                                     PIN_ODR_LOW(GPIOB_INT_N) |             \
417
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
418
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
419
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
420
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |          \
421
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
422
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
423
+                                     PIN_AFIO_AF(GPIOB_BUTTON, 0U) |        \
424
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \
425
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \
426
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0U) |          \
427
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
428
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_OUT_CTRL, 0U) |      \
429
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0U) |          \
430
+                                     PIN_AFIO_AF(GPIOB_SCL, 1U) |           \
431
+                                     PIN_AFIO_AF(GPIOB_SDA, 1U) |           \
432
+                                     PIN_AFIO_AF(GPIOB_INT_N, 0U) |         \
433
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U) |         \
434
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U) |         \
435
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))
436
+
437
+/*
438
+ * GPIOC setup:
439
+ *
440
+ * PC0  - PIN0                      (input pullup).
441
+ * PC1  - PIN1                      (input pullup).
442
+ * PC2  - PIN2                      (input pullup).
443
+ * PC3  - PIN3                      (input pullup).
444
+ * PC4  - PIN4                      (input pullup).
445
+ * PC5  - PIN5                      (input pullup).
446
+ * PC6  - PIN6                      (input pullup).
447
+ * PC7  - PIN7                      (input pullup).
448
+ * PC8  - PIN8                      (input pullup).
449
+ * PC9  - PIN9                      (input pullup).
450
+ * PC10 - PIN10                     (input pullup).
451
+ * PC11 - PIN11                     (input pullup).
452
+ * PC12 - PIN12                     (input pullup).
453
+ * PC13 - PIN13                     (input pullup).
454
+ * PC14 - PIN14                     (input pullup).
455
+ * PC15 - PIN15                     (input pullup).
456
+ */
457
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
458
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
459
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
460
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
461
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
462
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
463
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
464
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
465
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
466
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
467
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
468
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
469
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
470
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
471
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
472
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
473
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
474
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
475
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
476
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
477
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
478
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
479
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
480
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
481
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
482
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
483
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
484
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
485
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
486
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
487
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
488
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
489
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_PIN0) |          \
490
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN1) |       \
491
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN2) |       \
492
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN3) |       \
493
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN4) |       \
494
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN5) |       \
495
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN6) |       \
496
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN7) |       \
497
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN8) |       \
498
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN9) |       \
499
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN10) |      \
500
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN11) |      \
501
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN12) |      \
502
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN13) |      \
503
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN14) |      \
504
+                                     PIN_OSPEED_VERYLOW(GPIOC_PIN15))
505
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
506
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
507
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
508
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
509
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
510
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
511
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
512
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
513
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
514
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN9) |         \
515
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \
516
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
517
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
518
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
519
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \
520
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))
521
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
522
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
523
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
524
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
525
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
526
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
527
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
528
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
529
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
530
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
531
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
532
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
533
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
534
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
535
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
536
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
537
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0U) |          \
538
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0U) |          \
539
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0U) |          \
540
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0U) |          \
541
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0U) |          \
542
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0U) |          \
543
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0U) |          \
544
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0U))
545
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U) |          \
546
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0U) |          \
547
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0U) |         \
548
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0U) |         \
549
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0U) |         \
550
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0U) |         \
551
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0U) |         \
552
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0U))
553
+
554
+/*
555
+ * GPIOD setup:
556
+ *
557
+ * PD0  - PIN0                      (input pullup).
558
+ * PD1  - PIN1                      (input pullup).
559
+ * PD2  - PIN2                      (input pullup).
560
+ * PD3  - PIN3                      (input pullup).
561
+ * PD4  - PIN4                      (input pullup).
562
+ * PD5  - PIN5                      (input pullup).
563
+ * PD6  - PIN6                      (input pullup).
564
+ * PD7  - PIN7                      (input pullup).
565
+ * PD8  - PIN8                      (input pullup).
566
+ * PD9  - PIN9                      (input pullup).
567
+ * PD10 - PIN10                     (input pullup).
568
+ * PD11 - PIN11                     (input pullup).
569
+ * PD12 - PIN12                     (input pullup).
570
+ * PD13 - PIN13                     (input pullup).
571
+ * PD14 - PIN14                     (input pullup).
572
+ * PD15 - PIN15                     (input pullup).
573
+ */
574
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
575
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
576
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
577
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
578
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
579
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
580
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
581
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
582
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
583
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
584
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
585
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
586
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
587
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
588
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
589
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
590
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
591
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
592
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
593
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
594
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
595
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
596
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
597
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
598
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
599
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
600
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
601
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
602
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
603
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
604
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
605
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
606
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOD_PIN0) |       \
607
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN1) |       \
608
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN2) |       \
609
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN3) |       \
610
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN4) |       \
611
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN5) |       \
612
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN6) |       \
613
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN7) |       \
614
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN8) |       \
615
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN9) |       \
616
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN10) |      \
617
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN11) |      \
618
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN12) |      \
619
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN13) |      \
620
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN14) |      \
621
+                                     PIN_OSPEED_VERYLOW(GPIOD_PIN15))
622
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
623
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
624
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
625
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
626
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
627
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
628
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
629
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
630
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
631
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
632
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
633
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
634
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
635
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
636
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
637
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
638
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
639
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
640
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
641
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
642
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
643
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
644
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
645
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
646
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
647
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
648
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
649
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
650
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
651
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
652
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
653
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
654
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U) |          \
655
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0U) |          \
656
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0U) |          \
657
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0U) |          \
658
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0U) |          \
659
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0U) |          \
660
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0U) |          \
661
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0U))
662
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0U) |          \
663
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0U) |          \
664
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0U) |         \
665
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0U) |         \
666
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0U) |         \
667
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0U) |         \
668
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0U) |         \
669
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0U))
670
+
671
+/*
672
+ * GPIOE setup:
673
+ *
674
+ * PE0  - PIN0                      (input pullup).
675
+ * PE1  - PIN1                      (input pullup).
676
+ * PE2  - PIN2                      (input pullup).
677
+ * PE3  - PIN3                      (input pullup).
678
+ * PE4  - PIN4                      (input pullup).
679
+ * PE5  - PIN5                      (input pullup).
680
+ * PE6  - PIN6                      (input pullup).
681
+ * PE7  - PIN7                      (input pullup).
682
+ * PE8  - PIN8                      (input pullup).
683
+ * PE9  - PIN9                      (input pullup).
684
+ * PE10 - PIN10                     (input pullup).
685
+ * PE11 - PIN11                     (input pullup).
686
+ * PE12 - PIN12                     (input pullup).
687
+ * PE13 - PIN13                     (input pullup).
688
+ * PE14 - PIN14                     (input pullup).
689
+ * PE15 - PIN15                     (input pullup).
690
+ */
691
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_PIN0) |           \
692
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
693
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
694
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
695
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
696
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
697
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
698
+                                     PIN_MODE_INPUT(GPIOE_PIN7) |           \
699
+                                     PIN_MODE_INPUT(GPIOE_PIN8) |           \
700
+                                     PIN_MODE_INPUT(GPIOE_PIN9) |           \
701
+                                     PIN_MODE_INPUT(GPIOE_PIN10) |          \
702
+                                     PIN_MODE_INPUT(GPIOE_PIN11) |          \
703
+                                     PIN_MODE_INPUT(GPIOE_PIN12) |          \
704
+                                     PIN_MODE_INPUT(GPIOE_PIN13) |          \
705
+                                     PIN_MODE_INPUT(GPIOE_PIN14) |          \
706
+                                     PIN_MODE_INPUT(GPIOE_PIN15))
707
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) |       \
708
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
709
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
710
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
711
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
712
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
713
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
714
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7) |       \
715
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8) |       \
716
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9) |       \
717
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10) |      \
718
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11) |      \
719
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12) |      \
720
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13) |      \
721
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14) |      \
722
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
723
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOE_PIN0) |       \
724
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN1) |       \
725
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN2) |       \
726
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN3) |       \
727
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN4) |       \
728
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN5) |       \
729
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN6) |       \
730
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN7) |       \
731
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN8) |       \
732
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN9) |       \
733
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN10) |      \
734
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN11) |      \
735
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN12) |      \
736
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN13) |      \
737
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN14) |      \
738
+                                     PIN_OSPEED_VERYLOW(GPIOE_PIN15))
739
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_PULLUP(GPIOE_PIN0) |         \
740
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
741
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
742
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
743
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
744
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
745
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
746
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN7) |         \
747
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN8) |         \
748
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN9) |         \
749
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN10) |        \
750
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN11) |        \
751
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN12) |        \
752
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN13) |        \
753
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN14) |        \
754
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN15))
755
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0) |             \
756
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
757
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
758
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
759
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
760
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
761
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
762
+                                     PIN_ODR_HIGH(GPIOE_PIN7) |             \
763
+                                     PIN_ODR_HIGH(GPIOE_PIN8) |             \
764
+                                     PIN_ODR_HIGH(GPIOE_PIN9) |             \
765
+                                     PIN_ODR_HIGH(GPIOE_PIN10) |            \
766
+                                     PIN_ODR_HIGH(GPIOE_PIN11) |            \
767
+                                     PIN_ODR_HIGH(GPIOE_PIN12) |            \
768
+                                     PIN_ODR_HIGH(GPIOE_PIN13) |            \
769
+                                     PIN_ODR_HIGH(GPIOE_PIN14) |            \
770
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
771
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0U) |          \
772
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0U) |          \
773
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0U) |          \
774
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0U) |          \
775
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0U) |          \
776
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0U) |          \
777
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0U) |          \
778
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0U))
779
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0U) |          \
780
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0U) |          \
781
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0U) |         \
782
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0U) |         \
783
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0U) |         \
784
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0U) |         \
785
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0U) |         \
786
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0U))
787
+
788
+/*
789
+ * GPIOF setup:
790
+ *
791
+ * PF0  - PIN0                      (input pullup).
792
+ * PF1  - PIN1                      (input pullup).
793
+ * PF2  - PIN2                      (input pullup).
794
+ * PF3  - PIN3                      (input pullup).
795
+ * PF4  - PIN4                      (input pullup).
796
+ * PF5  - PIN5                      (input pullup).
797
+ * PF6  - PIN6                      (input pullup).
798
+ * PF7  - PIN7                      (input pullup).
799
+ * PF8  - PIN8                      (input pullup).
800
+ * PF9  - PIN9                      (input pullup).
801
+ * PF10 - PIN10                     (input pullup).
802
+ * PF11 - PIN11                     (input pullup).
803
+ * PF12 - PIN12                     (input pullup).
804
+ * PF13 - PIN13                     (input pullup).
805
+ * PF14 - PIN14                     (input pullup).
806
+ * PF15 - PIN15                     (input pullup).
807
+ */
808
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
809
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
810
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
811
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
812
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
813
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
814
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
815
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
816
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
817
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
818
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
819
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
820
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
821
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
822
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
823
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
824
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
825
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
826
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
827
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
828
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
829
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
830
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
831
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
832
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
833
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
834
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
835
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
836
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
837
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
838
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
839
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
840
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_VERYLOW(GPIOF_PIN0) |       \
841
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN1) |       \
842
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN2) |       \
843
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN3) |       \
844
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN4) |       \
845
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN5) |       \
846
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN6) |       \
847
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN7) |       \
848
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN8) |       \
849
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN9) |       \
850
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN10) |      \
851
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN11) |      \
852
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN12) |      \
853
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN13) |      \
854
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN14) |      \
855
+                                     PIN_OSPEED_VERYLOW(GPIOF_PIN15))
856
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |         \
857
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |         \
858
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
859
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
860
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
861
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
862
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
863
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
864
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
865
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
866
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
867
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
868
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
869
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
870
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
871
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
872
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
873
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
874
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
875
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
876
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
877
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
878
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
879
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
880
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
881
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
882
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
883
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
884
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
885
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
886
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
887
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
888
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U) |          \
889
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0U) |          \
890
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0U) |          \
891
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0U) |          \
892
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0U) |          \
893
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0U) |          \
894
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0U) |          \
895
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0U))
896
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U) |          \
897
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0U) |          \
898
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0U) |         \
899
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0U) |         \
900
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0U) |         \
901
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0U) |         \
902
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0U) |         \
903
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0U))
904
+
905
+
906
+#if !defined(_FROM_ASM_)
907
+#ifdef __cplusplus
908
+extern "C" {
909
+#endif
910
+  void boardInit(void);
911
+#ifdef __cplusplus
912
+}
913
+#endif
914
+#endif /* _FROM_ASM_ */
915
+
916
+#endif /* BOARD_H */

+ 5
- 0
boards/PD_BUDDY/board.mk View File

@@ -0,0 +1,5 @@
1
+# List of all the board related files.
2
+BOARDSRC = $(CHIBIOS)/../boards/PD_BUDDY/board.c
3
+
4
+# Required include directories
5
+BOARDINC = $(CHIBIOS)/../boards/PD_BUDDY

+ 703
- 0
boards/PD_BUDDY/cfg/board.chcfg View File

@@ -0,0 +1,703 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!--PD Buddy ChibiOS board configuration-->
3
+<board
4
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
5
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f0xx_board.xsd">
6
+  <configuration_settings>
7
+    <templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
8
+    <output_path>..</output_path>
9
+    <hal_version>3.0.x</hal_version>
10
+  </configuration_settings>
11
+  <board_name>PD Buddy</board_name>
12
+  <board_id>PD_BUDDY</board_id>
13
+  <board_functions></board_functions>
14
+  <subtype>STM32F072xB</subtype>
15
+  <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
16
+  	LSEBypass="false" LSEDrive="3 High Drive (default)" />
17
+  <ports>
18
+    <GPIOA>
19
+      <pin0
20
+        ID=""
21
+        Type="PushPull"
22
+        Speed="Minimum"
23
+        Resistor="PullUp"
24
+        Level="High"
25
+        Mode="Input"
26
+        Alternate="0" />
27
+      <pin1
28
+        ID=""
29
+        Type="PushPull"
30
+        Speed="Minimum"
31
+        Resistor="PullUp"
32
+        Level="High"
33
+        Mode="Input"
34
+        Alternate="0" />
35
+      <pin2
36
+        ID=""
37
+        Type="PushPull"
38
+        Speed="Minimum"
39
+        Resistor="PullUp"
40
+        Level="High"
41
+        Mode="Input"
42
+        Alternate="0" />
43
+      <pin3
44
+        ID=""
45
+        Type="PushPull"
46
+        Speed="Minimum"
47
+        Resistor="PullUp"
48
+        Level="High"
49
+        Mode="Input"
50
+        Alternate="0" />
51
+      <pin4
52
+        ID=""
53
+        Type="PushPull"
54
+        Speed="Minimum"
55
+        Resistor="PullUp"
56
+        Level="High"
57
+        Mode="Input"
58
+        Alternate="0" />
59
+      <pin5
60
+        ID=""
61
+        Type="PushPull"
62
+        Speed="Minimum"
63
+        Resistor="PullUp"
64
+        Level="High"
65
+        Mode="Input"
66
+        Alternate="0" />
67
+      <pin6
68
+        ID=""
69
+        Type="PushPull"
70
+        Speed="Minimum"
71
+        Resistor="PullUp"
72
+        Level="High"
73
+        Mode="Input"
74
+        Alternate="0" />
75
+      <pin7
76
+        ID=""
77
+        Type="PushPull"
78
+        Speed="Minimum"
79
+        Resistor="PullUp"
80
+        Level="High"
81
+        Mode="Input"
82
+        Alternate="0" />
83
+      <pin8
84
+        ID=""
85
+        Type="PushPull"
86
+        Speed="Minimum"
87
+        Resistor="PullUp"
88
+        Level="High"
89
+        Mode="Input"
90
+        Alternate="0" />
91
+      <pin9
92
+        ID=""
93
+        Type="PushPull"
94
+        Speed="Minimum"
95
+        Resistor="PullUp"
96
+        Level="High"
97
+        Mode="Input"
98
+        Alternate="0" />
99
+      <pin10
100
+        ID=""
101
+        Type="PushPull"
102
+        Speed="Minimum"
103
+        Resistor="PullUp"
104
+        Level="High"
105
+        Mode="Input"
106
+        Alternate="0" />
107
+      <pin11
108
+        ID="USB_DM"
109
+        Type="PushPull"
110
+        Speed="Minimum"
111
+        Resistor="Floating"
112
+        Level="High"
113
+        Mode="Input"
114
+        Alternate="0" />
115
+      <pin12
116
+        ID="USB_DP"
117
+        Type="PushPull"
118
+        Speed="Minimum"
119
+        Resistor="Floating"
120
+        Level="High"
121
+        Mode="Input"
122
+        Alternate="0" />
123
+      <pin13
124
+        ID="SWDIO"
125
+        Type="PushPull"
126
+        Speed="Maximum"
127
+        Resistor="PullUp"
128
+        Level="High"
129
+        Mode="Alternate"
130
+        Alternate="0" />
131
+      <pin14
132
+        ID="SWCLK"
133
+        Type="PushPull"
134
+        Speed="Maximum"
135
+        Resistor="PullDown"
136
+        Level="High"
137
+        Mode="Alternate"
138
+        Alternate="0" />
139
+      <pin15
140
+        ID="LED"
141
+        Type="PushPull"
142
+        Speed="Maximum"
143
+        Resistor="Floating"
144
+        Level="Low"
145
+        Mode="Output"
146
+        Alternate="0" />
147
+    </GPIOA>
148
+    <GPIOB>
149
+      <pin0
150
+        ID=""
151
+        Type="PushPull"
152
+        Speed="Minimum"
153
+        Resistor="PullUp"
154
+        Level="High"
155
+        Mode="Input"
156
+        Alternate="0" />
157
+      <pin1
158
+        ID=""
159
+        Type="PushPull"
160
+        Speed="Minimum"
161
+        Resistor="PullUp"
162
+        Level="High"
163
+        Mode="Input"
164
+        Alternate="0" />
165
+      <pin2
166
+        ID=""
167
+        Type="PushPull"
168
+        Speed="Maximum"
169
+        Resistor="PullUp"
170
+        Level="High"
171
+        Mode="Input"
172
+        Alternate="0" />
173
+      <pin3
174
+        ID="BUTTON"
175
+        Type="PushPull"
176
+        Speed="Minimum"
177
+        Resistor="Floating"
178
+        Level="High"
179
+        Mode="Input"
180
+        Alternate="0" />
181
+      <pin4
182
+        ID=""
183
+        Type="PushPull"
184
+        Speed="Maximum"
185
+        Resistor="PullUp"
186
+        Level="High"
187
+        Mode="Input"
188
+        Alternate="0" />
189
+      <pin5
190
+        ID=""
191
+        Type="PushPull"
192
+        Speed="Minimum"
193
+        Resistor="PullUp"
194
+        Level="High"
195
+        Mode="Input"
196
+        Alternate="0" />
197
+      <pin6
198
+        ID=""
199
+        Type="PushPull"
200
+        Speed="Minimum"
201
+        Resistor="PullUp"
202
+        Level="High"
203
+        Mode="Input"
204
+        Alternate="0" />
205
+      <pin7
206
+        ID=""
207
+        Type="PushPull"
208
+        Speed="Minimum"
209
+        Resistor="PullUp"
210
+        Level="High"
211
+        Mode="Input"
212
+        Alternate="0" />
213
+      <pin8
214
+        ID="OUT_CTRL"
215
+        Type="PushPull"
216
+        Speed="Minimum"
217
+        Resistor="Floating"
218
+        Level="Low"
219
+        Mode="Output"
220
+        Alternate="0" />
221
+      <pin9
222
+        ID=""
223
+        Type="PushPull"
224
+        Speed="Minimum"
225
+        Resistor="PullUp"
226
+        Level="High"
227
+        Mode="Input"
228
+        Alternate="0" />
229
+      <pin10
230
+        ID="SCL"
231
+        Type="OpenDrain"
232
+        Speed="Maximum"
233
+        Resistor="Floating"
234
+        Level="High"
235
+        Mode="Alternate"
236
+        Alternate="1" />
237
+      <pin11
238
+        ID="SDA"
239
+        Type="OpenDrain"
240
+        Speed="Maximum"
241
+        Resistor="Floating"
242
+        Level="High"
243
+        Mode="Alternate"
244
+        Alternate="1" />
245
+      <pin12
246
+        ID="INT_N"
247
+        Type="PushPull"
248
+        Speed="High"
249
+        Resistor="Floating"
250
+        Level="Low"
251
+        Mode="Input"
252
+        Alternate="0" />
253
+      <pin13
254
+        ID=""
255
+        Type="PushPull"
256
+        Speed="Minimum"
257
+        Resistor="PullUp"
258
+        Level="High"
259
+        Mode="Input"
260
+        Alternate="0" ></pin13>
261
+      <pin14
262
+        ID=""
263
+        Type="PushPull"
264
+        Speed="Minimum"
265
+        Resistor="PullUp"
266
+        Level="High"
267
+        Mode="Input"
268
+        Alternate="0" />
269
+      <pin15
270
+        ID=""
271
+        Type="PushPull"
272
+        Speed="Minimum"
273
+        Resistor="PullUp"
274
+        Level="High"
275
+        Mode="Input"
276
+        Alternate="0" />
277
+    </GPIOB>
278
+    <GPIOC>
279
+      <pin0
280
+        ID=""
281
+        Type="PushPull"
282
+        Speed="Maximum"
283
+        Resistor="PullUp"
284
+        Level="High"
285
+        Mode="Input"
286
+        Alternate="0" />
287
+      <pin1
288
+        ID=""
289
+        Type="PushPull"
290
+        Speed="Minimum"
291
+        Resistor="PullUp"
292
+        Level="High"
293
+        Mode="Input"
294
+        Alternate="0" />
295
+      <pin2
296
+        ID=""
297
+        Type="PushPull"
298
+        Speed="Minimum"
299
+        Resistor="PullUp"
300
+        Level="High"
301
+        Mode="Input"
302
+        Alternate="0" />
303
+      <pin3
304
+        ID=""
305
+        Type="PushPull"
306
+        Speed="Minimum"
307
+        Resistor="PullUp"
308
+        Level="High"
309
+        Mode="Input"
310
+        Alternate="0" />
311
+      <pin4
312
+        ID=""
313
+        Type="PushPull"
314
+        Speed="Minimum"
315
+        Resistor="PullUp"
316
+        Level="High"
317
+        Mode="Input"
318
+        Alternate="0" />
319
+      <pin5
320
+        ID=""
321
+        Type="PushPull"
322
+        Speed="Minimum"
323
+        Resistor="PullUp"
324
+        Level="High"
325
+        Mode="Input"
326
+        Alternate="0" />
327
+      <pin6
328
+        ID=""
329
+        Type="PushPull"
330
+        Speed="Minimum"
331
+        Resistor="PullUp"
332
+        Level="High"
333
+        Mode="Input"
334
+        Alternate="0" />
335
+      <pin7
336
+        ID=""
337
+        Type="PushPull"
338
+        Speed="Minimum"
339
+        Resistor="PullUp"
340
+        Level="High"
341
+        Mode="Input"
342
+        Alternate="0" />
343
+      <pin8
344
+        ID=""
345
+        Type="PushPull"
346
+        Speed="Minimum"
347
+        Resistor="PullUp"
348
+        Level="High"
349
+        Mode="Input"
350
+        Alternate="0" ></pin8>
351
+      <pin9
352
+        ID=""
353
+        Type="PushPull"
354
+        Speed="Minimum"
355
+        Resistor="PullUp"
356
+        Level="High"
357
+        Mode="Input"
358
+        Alternate="0" />
359
+      <pin10
360
+        ID=""
361
+        Type="PushPull"
362
+        Speed="Minimum"
363
+        Resistor="PullUp"
364
+        Level="High"
365
+        Mode="Input"
366
+        Alternate="0" />
367
+      <pin11
368
+        ID=""
369
+        Type="PushPull"
370
+        Speed="Minimum"
371
+        Resistor="PullUp"
372
+        Level="High"
373
+        Mode="Input"
374
+        Alternate="0" />
375
+      <pin12
376
+        ID=""
377
+        Type="PushPull"
378
+        Speed="Minimum"
379
+        Resistor="PullUp"
380
+        Level="High"
381
+        Mode="Input"
382
+        Alternate="0" />
383
+      <pin13
384
+        ID=""
385
+        Type="PushPull"
386
+        Speed="Minimum"
387
+        Resistor="PullUp"
388
+        Level="High"
389
+        Mode="Input"
390
+        Alternate="0" />
391
+      <pin14
392
+        ID=""
393
+        Type="PushPull"
394
+        Speed="Minimum"
395
+        Resistor="PullUp"
396
+        Level="High"
397
+        Mode="Input"
398
+        Alternate="0" />
399
+      <pin15
400
+        ID=""
401
+        Type="PushPull"
402
+        Speed="Minimum"
403
+        Resistor="PullUp"
404
+        Level="High"
405
+        Mode="Input"
406
+        Alternate="0" />
407
+    </GPIOC>
408
+    <GPIOD>
409
+      <pin0
410
+        ID=""
411
+        Type="PushPull"
412
+        Speed="Minimum"
413
+        Resistor="PullUp"
414
+        Level="High"
415
+        Mode="Input"
416
+        Alternate="0" />
417
+      <pin1
418
+        ID=""
419
+        Type="PushPull"
420
+        Speed="Minimum"
421
+        Resistor="PullUp"
422
+        Level="High"
423
+        Mode="Input"
424
+        Alternate="0" />
425
+      <pin2
426
+        ID=""
427
+        Type="PushPull"
428
+        Speed="Minimum"
429
+        Resistor="PullUp"
430
+        Level="High"
431
+        Mode="Input"
432
+        Alternate="0" />
433
+      <pin3
434
+        ID=""
435
+        Type="PushPull"
436
+        Speed="Minimum"
437
+        Resistor="PullUp"
438
+        Level="High"
439
+        Mode="Input"
440
+        Alternate="0" />
441
+      <pin4
442
+        ID=""
443
+        Type="PushPull"
444
+        Speed="Minimum"
445
+        Resistor="PullUp"
446
+        Level="High"
447
+        Mode="Input"
448
+        Alternate="0" />
449
+      <pin5
450
+        ID=""
451
+        Type="PushPull"
452
+        Speed="Minimum"
453
+        Resistor="PullUp"
454
+        Level="High"
455
+        Mode="Input"
456
+        Alternate="0" />
457
+      <pin6
458
+        ID=""
459
+        Type="PushPull"
460
+        Speed="Minimum"
461
+        Resistor="PullUp"
462
+        Level="High"
463
+        Mode="Input"
464
+        Alternate="0" />
465
+      <pin7
466
+        ID=""
467
+        Type="PushPull"
468
+        Speed="Minimum"
469
+        Resistor="PullUp"
470
+        Level="High"
471
+        Mode="Input"
472
+        Alternate="0" />
473
+      <pin8
474
+        ID=""
475
+        Type="PushPull"
476
+        Speed="Minimum"
477
+        Resistor="PullUp"
478
+        Level="High"
479
+        Mode="Input"
480
+        Alternate="0" />
481
+      <pin9
482
+        ID=""
483
+        Type="PushPull"
484
+        Speed="Minimum"
485
+        Resistor="PullUp"
486
+        Level="High"
487
+        Mode="Input"
488
+        Alternate="0" />
489
+      <pin10
490
+        ID=""
491
+        Type="PushPull"
492
+        Speed="Minimum"
493
+        Resistor="PullUp"
494
+        Level="High"
495
+        Mode="Input"
496
+        Alternate="0" />
497
+      <pin11
498
+        ID=""
499
+        Type="PushPull"
500
+        Speed="Minimum"
501
+        Resistor="PullUp"
502
+        Level="High"
503
+        Mode="Input"
504
+        Alternate="0" />
505
+      <pin12
506
+        ID=""
507
+        Type="PushPull"
508
+        Speed="Minimum"
509
+        Resistor="PullUp"
510
+        Level="High"
511
+        Mode="Input"
512
+        Alternate="0" />
513
+      <pin13
514
+        ID=""
515
+        Type="PushPull"
516
+        Speed="Minimum"
517
+        Resistor="PullUp"
518
+        Level="High"
519
+        Mode="Input"
520
+        Alternate="0" />
521
+      <pin14
522
+        ID=""
523
+        Type="PushPull"
524
+        Speed="Minimum"
525
+        Resistor="PullUp"
526
+        Level="High"
527
+        Mode="Input"
528
+        Alternate="0" />
529
+      <pin15
530
+        ID=""
531
+        Type="PushPull"
532
+        Speed="Minimum"
533
+        Resistor="PullUp"
534
+        Level="High"
535
+        Mode="Input"
536
+        Alternate="0" />
537
+    </GPIOD>
538
+    <GPIOE>
539
+    	<pin0 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
540
+    		Level="High" Mode="Input" Alternate="0" />
541
+    	<pin1 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
542
+    		Level="High" Mode="Input" Alternate="0" />
543
+    	<pin2 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
544
+    		Level="High" Mode="Input" Alternate="0" />
545
+    	<pin3 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
546
+    		Level="High" Mode="Input" Alternate="0" />
547
+    	<pin4 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
548
+    		Level="High" Mode="Input" Alternate="0" />
549
+    	<pin5 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
550
+    		Level="High" Mode="Input" Alternate="0" />
551
+    	<pin6 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
552
+    		Level="High" Mode="Input" Alternate="0" />
553
+    	<pin7 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
554
+    		Level="High" Mode="Input" Alternate="0" />
555
+    	<pin8 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
556
+    		Level="High" Mode="Input" Alternate="0" />
557
+    	<pin9 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
558
+    		Level="High" Mode="Input" Alternate="0" />
559
+    	<pin10 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
560
+    		Level="High" Mode="Input" Alternate="0" />
561
+    	<pin11 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
562
+    		Level="High" Mode="Input" Alternate="0" />
563
+    	<pin12 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
564
+    		Level="High" Mode="Input" Alternate="0" />
565
+    	<pin13 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
566
+    		Level="High" Mode="Input" Alternate="0" />
567
+    	<pin14 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
568
+    		Level="High" Mode="Input" Alternate="0" />
569
+    	<pin15 ID="" Type="PushPull" Speed="Minimum" Resistor="PullUp"
570
+    		Level="High" Mode="Input" Alternate="0" />
571
+    </GPIOE>
572
+    <GPIOF>
573
+      <pin0
574
+        ID=""
575
+        Type="PushPull"
576
+        Speed="Minimum"
577
+        Resistor="PullUp"
578
+        Level="High"
579
+        Mode="Input"
580
+        Alternate="0" />
581
+      <pin1
582
+        ID=""
583
+        Type="PushPull"
584
+        Speed="Minimum"
585
+        Resistor="PullUp"
586
+        Level="High"
587
+        Mode="Input"
588
+        Alternate="0" />
589
+      <pin2
590
+        ID=""
591
+        Type="PushPull"
592
+        Speed="Minimum"
593
+        Resistor="PullUp"
594
+        Level="High"
595
+        Mode="Input"
596
+        Alternate="0" />
597
+      <pin3
598
+        ID=""
599
+        Type="PushPull"
600
+        Speed="Minimum"
601
+        Resistor="PullUp"
602
+        Level="High"
603
+        Mode="Input"
604
+        Alternate="0" />
605
+      <pin4
606
+        ID=""
607
+        Type="PushPull"
608
+        Speed="Minimum"
609
+        Resistor="PullUp"
610
+        Level="High"
611
+        Mode="Input"
612
+        Alternate="0" />
613
+      <pin5
614
+        ID=""
615
+        Type="PushPull"
616
+        Speed="Minimum"
617
+        Resistor="PullUp"
618
+        Level="High"
619
+        Mode="Input"
620
+        Alternate="0" />
621
+      <pin6
622
+        ID=""
623
+        Type="PushPull"
624
+        Speed="Minimum"
625
+        Resistor="PullUp"
626
+        Level="High"
627
+        Mode="Input"
628
+        Alternate="0" />
629
+      <pin7
630
+        ID=""
631
+        Type="PushPull"
632
+        Speed="Minimum"
633
+        Resistor="PullUp"
634
+        Level="High"
635
+        Mode="Input"
636
+        Alternate="0" />
637
+      <pin8
638
+        ID=""
639
+        Type="PushPull"
640
+        Speed="Minimum"
641
+        Resistor="PullUp"
642
+        Level="High"
643
+        Mode="Input"
644
+        Alternate="0" />
645
+      <pin9
646
+        ID=""
647
+        Type="PushPull"
648
+        Speed="Minimum"
649
+        Resistor="PullUp"
650
+        Level="High"
651
+        Mode="Input"
652
+        Alternate="0" />
653
+      <pin10
654
+        ID=""
655
+        Type="PushPull"
656
+        Speed="Minimum"
657
+        Resistor="PullUp"
658
+        Level="High"
659
+        Mode="Input"
660
+        Alternate="0" />
661
+      <pin11
662
+        ID=""
663
+        Type="PushPull"
664
+        Speed="Minimum"
665
+        Resistor="PullUp"
666
+        Level="High"
667
+        Mode="Input"
668
+        Alternate="0" />
669
+      <pin12
670
+        ID=""
671
+        Type="PushPull"
672
+        Speed="Minimum"
673
+        Resistor="PullUp"
674
+        Level="High"
675
+        Mode="Input"
676
+        Alternate="0" />
677
+      <pin13
678
+        ID=""
679
+        Type="PushPull"
680
+        Speed="Minimum"
681
+        Resistor="PullUp"
682
+        Level="High"
683
+        Mode="Input"
684
+        Alternate="0" />
685
+      <pin14
686
+        ID=""
687
+        Type="PushPull"
688
+        Speed="Minimum"
689
+        Resistor="PullUp"
690
+        Level="High"
691
+        Mode="Input"
692
+        Alternate="0" />
693
+      <pin15
694
+        ID=""
695
+        Type="PushPull"
696
+        Speed="Minimum"
697
+        Resistor="PullUp"
698
+        Level="High"
699
+        Mode="Input"
700
+        Alternate="0" />
701
+    </GPIOF>
702
+  </ports>
703
+</board>

+ 499
- 0
chconf.h View File

@@ -0,0 +1,499 @@
1
+/*
2
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3
+
4
+    Licensed under the Apache License, Version 2.0 (the "License");
5
+    you may not use this file except in compliance with the License.
6
+    You may obtain a copy of the License at
7
+
8
+        http://www.apache.org/licenses/LICENSE-2.0
9
+
10
+    Unless required by applicable law or agreed to in writing, software
11
+    distributed under the License is distributed on an "AS IS" BASIS,
12
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+    See the License for the specific language governing permissions and
14
+    limitations under the License.
15
+*/
16
+
17
+/**
18
+ * @file    templates/chconf.h
19
+ * @brief   Configuration file template.
20
+ * @details A copy of this file must be placed in each project directory, it
21
+ *          contains the application specific kernel settings.
22
+ *
23
+ * @addtogroup config
24
+ * @details Kernel related settings and hooks.
25
+ * @{
26
+ */
27
+
28
+#ifndef _CHCONF_H_
29
+#define _CHCONF_H_
30
+
31
+/*===========================================================================*/
32
+/**
33
+ * @name System timers settings
34
+ * @{
35
+ */
36
+/*===========================================================================*/
37
+
38
+/**
39
+ * @brief   System time counter resolution.
40
+ * @note    Allowed values are 16 or 32 bits.
41
+ */
42
+#define CH_CFG_ST_RESOLUTION                32
43
+
44
+/**
45
+ * @brief   System tick frequency.
46
+ * @details Frequency of the system timer that drives the system ticks. This
47
+ *          setting also defines the system tick time unit.
48
+ */
49
+#define CH_CFG_ST_FREQUENCY                 10000
50
+
51
+/**
52
+ * @brief   Time delta constant for the tick-less mode.
53
+ * @note    If this value is zero then the system uses the classic
54
+ *          periodic tick. This value represents the minimum number
55
+ *          of ticks that is safe to specify in a timeout directive.
56
+ *          The value one is not valid, timeouts are rounded up to
57
+ *          this value.
58
+ */
59
+#define CH_CFG_ST_TIMEDELTA                 2
60
+
61
+/** @} */
62
+
63
+/*===========================================================================*/
64
+/**
65
+ * @name Kernel parameters and options
66
+ * @{
67
+ */
68
+/*===========================================================================*/
69
+
70
+/**
71
+ * @brief   Round robin interval.
72
+ * @details This constant is the number of system ticks allowed for the
73
+ *          threads before preemption occurs. Setting this value to zero
74
+ *          disables the preemption for threads with equal priority and the
75
+ *          round robin becomes cooperative. Note that higher priority
76
+ *          threads can still preempt, the kernel is always preemptive.
77
+ * @note    Disabling the round robin preemption makes the kernel more compact
78
+ *          and generally faster.
79
+ * @note    The round robin preemption is not supported in tickless mode and
80
+ *          must be set to zero in that case.
81
+ */
82
+#define CH_CFG_TIME_QUANTUM                 0
83
+
84
+/**
85
+ * @brief   Managed RAM size.
86
+ * @details Size of the RAM area to be managed by the OS. If set to zero
87
+ *          then the whole available RAM is used. The core memory is made
88
+ *          available to the heap allocator and/or can be used directly through
89
+ *          the simplified core memory allocator.
90
+ *
91
+ * @note    In order to let the OS manage the whole RAM the linker script must
92
+ *          provide the @p __heap_base__ and @p __heap_end__ symbols.
93
+ * @note    Requires @p CH_CFG_USE_MEMCORE.
94
+ */
95
+#define CH_CFG_MEMCORE_SIZE                 0
96
+
97
+/**
98
+ * @brief   Idle thread automatic spawn suppression.
99
+ * @details When this option is activated the function @p chSysInit()
100
+ *          does not spawn the idle thread. The application @p main()
101
+ *          function becomes the idle thread and must implement an
102
+ *          infinite loop.
103
+ */
104
+#define CH_CFG_NO_IDLE_THREAD               FALSE
105
+
106
+/** @} */
107
+
108
+/*===========================================================================*/
109
+/**
110
+ * @name Performance options
111
+ * @{
112
+ */
113
+/*===========================================================================*/
114
+
115
+/**
116
+ * @brief   OS optimization.
117
+ * @details If enabled then time efficient rather than space efficient code
118
+ *          is used when two possible implementations exist.
119
+ *
120
+ * @note    This is not related to the compiler optimization options.
121
+ * @note    The default is @p TRUE.
122
+ */
123
+#define CH_CFG_OPTIMIZE_SPEED               TRUE
124
+
125
+/** @} */
126
+
127
+/*===========================================================================*/
128
+/**
129
+ * @name Subsystem options
130
+ * @{
131
+ */
132
+/*===========================================================================*/
133
+
134
+/**
135
+ * @brief   Time Measurement APIs.
136
+ * @details If enabled then the time measurement APIs are included in
137
+ *          the kernel.
138
+ *
139
+ * @note    The default is @p TRUE.
140
+ */
141
+#define CH_CFG_USE_TM                       FALSE
142
+
143
+/**
144
+ * @brief   Threads registry APIs.
145
+ * @details If enabled then the registry APIs are included in the kernel.
146
+ *
147
+ * @note    The default is @p TRUE.
148
+ */
149
+#define CH_CFG_USE_REGISTRY                 TRUE
150
+
151
+/**
152
+ * @brief   Threads synchronization APIs.
153
+ * @details If enabled then the @p chThdWait() function is included in
154
+ *          the kernel.
155
+ *
156
+ * @note    The default is @p TRUE.
157
+ */
158
+#define CH_CFG_USE_WAITEXIT                 TRUE
159
+
160
+/**
161
+ * @brief   Semaphores APIs.
162
+ * @details If enabled then the Semaphores APIs are included in the kernel.
163
+ *
164
+ * @note    The default is @p TRUE.
165
+ */
166
+#define CH_CFG_USE_SEMAPHORES               TRUE
167
+
168
+/**
169
+ * @brief   Semaphores queuing mode.
170
+ * @details If enabled then the threads are enqueued on semaphores by
171
+ *          priority rather than in FIFO order.
172
+ *
173
+ * @note    The default is @p FALSE. Enable this if you have special
174
+ *          requirements.
175
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
176
+ */
177
+#define CH_CFG_USE_SEMAPHORES_PRIORITY      FALSE
178
+
179
+/**
180
+ * @brief   Mutexes APIs.
181
+ * @details If enabled then the mutexes APIs are included in the kernel.
182
+ *
183
+ * @note    The default is @p TRUE.
184
+ */
185
+#define CH_CFG_USE_MUTEXES                  TRUE
186
+
187
+/**
188
+ * @brief   Enables recursive behavior on mutexes.
189
+ * @note    Recursive mutexes are heavier and have an increased
190
+ *          memory footprint.
191
+ *
192
+ * @note    The default is @p FALSE.
193
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
194
+ */
195
+#define CH_CFG_USE_MUTEXES_RECURSIVE        FALSE
196
+
197
+/**
198
+ * @brief   Conditional Variables APIs.
199
+ * @details If enabled then the conditional variables APIs are included
200
+ *          in the kernel.
201
+ *
202
+ * @note    The default is @p TRUE.
203
+ * @note    Requires @p CH_CFG_USE_MUTEXES.
204
+ */
205
+#define CH_CFG_USE_CONDVARS                 TRUE
206
+
207
+/**
208
+ * @brief   Conditional Variables APIs with timeout.
209
+ * @details If enabled then the conditional variables APIs with timeout
210
+ *          specification are included in the kernel.
211
+ *
212
+ * @note    The default is @p TRUE.
213
+ * @note    Requires @p CH_CFG_USE_CONDVARS.
214
+ */
215
+#define CH_CFG_USE_CONDVARS_TIMEOUT         TRUE
216
+
217
+/**
218
+ * @brief   Events Flags APIs.
219
+ * @details If enabled then the event flags APIs are included in the kernel.
220
+ *
221
+ * @note    The default is @p TRUE.
222
+ */
223
+#define CH_CFG_USE_EVENTS                   TRUE
224
+
225
+/**
226
+ * @brief   Events Flags APIs with timeout.
227
+ * @details If enabled then the events APIs with timeout specification
228
+ *          are included in the kernel.
229
+ *
230
+ * @note    The default is @p TRUE.
231
+ * @note    Requires @p CH_CFG_USE_EVENTS.
232
+ */
233
+#define CH_CFG_USE_EVENTS_TIMEOUT           TRUE
234
+
235
+/**
236
+ * @brief   Synchronous Messages APIs.
237
+ * @details If enabled then the synchronous messages APIs are included
238
+ *          in the kernel.
239
+ *
240
+ * @note    The default is @p TRUE.
241
+ */
242
+#define CH_CFG_USE_MESSAGES                 TRUE
243
+
244
+/**
245
+ * @brief   Synchronous Messages queuing mode.
246
+ * @details If enabled then messages are served by priority rather than in
247
+ *          FIFO order.
248
+ *
249
+ * @note    The default is @p FALSE. Enable this if you have special
250
+ *          requirements.
251
+ * @note    Requires @p CH_CFG_USE_MESSAGES.
252
+ */
253
+#define CH_CFG_USE_MESSAGES_PRIORITY        FALSE
254
+
255
+/**
256
+ * @brief   Mailboxes APIs.
257
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
258
+ *          included in the kernel.
259
+ *
260
+ * @note    The default is @p TRUE.
261
+ * @note    Requires @p CH_CFG_USE_SEMAPHORES.
262
+ */
263
+#define CH_CFG_USE_MAILBOXES                TRUE
264
+
265
+/**
266
+ * @brief   I/O Queues APIs.
267
+ * @details If enabled then the I/O queues APIs are included in the kernel.
268
+ *
269
+ * @note    The default is @p TRUE.
270
+ */
271
+#define CH_CFG_USE_QUEUES                   TRUE
272
+
273
+/**
274
+ * @brief   Core Memory Manager APIs.
275
+ * @details If enabled then the core memory manager APIs are included
276
+ *          in the kernel.
277
+ *
278
+ * @note    The default is @p TRUE.
279
+ */
280
+#define CH_CFG_USE_MEMCORE                  TRUE
281
+
282
+/**
283
+ * @brief   Heap Allocator APIs.
284
+ * @details If enabled then the memory heap allocator APIs are included
285
+ *          in the kernel.
286
+ *
287
+ * @note    The default is @p TRUE.
288
+ * @note    Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
289
+ *          @p CH_CFG_USE_SEMAPHORES.
290
+ * @note    Mutexes are recommended.
291
+ */
292
+#define CH_CFG_USE_HEAP                     TRUE
293
+
294
+/**
295
+ * @brief   Memory Pools Allocator APIs.
296
+ * @details If enabled then the memory pools allocator APIs are included
297
+ *          in the kernel.
298
+ *
299
+ * @note    The default is @p TRUE.
300
+ */
301
+#define CH_CFG_USE_MEMPOOLS                 TRUE
302
+
303
+/**
304
+ * @brief   Dynamic Threads APIs.
305
+ * @details If enabled then the dynamic threads creation APIs are included
306
+ *          in the kernel.
307
+ *
308
+ * @note    The default is @p TRUE.
309
+ * @note    Requires @p CH_CFG_USE_WAITEXIT.
310
+ * @note    Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
311
+ */
312
+#define CH_CFG_USE_DYNAMIC                  TRUE
313
+
314
+/** @} */
315
+
316
+/*===========================================================================*/
317
+/**
318
+ * @name Debug options
319
+ * @{
320
+ */
321
+/*===========================================================================*/
322
+
323
+/**
324
+ * @brief   Debug option, kernel statistics.
325
+ *
326
+ * @note    The default is @p FALSE.
327
+ */
328
+#define CH_DBG_STATISTICS                   FALSE
329
+
330
+/**
331
+ * @brief   Debug option, system state check.
332
+ * @details If enabled the correct call protocol for system APIs is checked
333
+ *          at runtime.
334
+ *
335
+ * @note    The default is @p FALSE.
336
+ */
337
+#define CH_DBG_SYSTEM_STATE_CHECK           TRUE
338
+
339
+/**
340
+ * @brief   Debug option, parameters checks.
341
+ * @details If enabled then the checks on the API functions input
342
+ *          parameters are activated.
343
+ *
344
+ * @note    The default is @p FALSE.
345
+ */
346
+#define CH_DBG_ENABLE_CHECKS                TRUE
347
+
348
+/**
349
+ * @brief   Debug option, consistency checks.
350
+ * @details If enabled then all the assertions in the kernel code are
351
+ *          activated. This includes consistency checks inside the kernel,
352
+ *          runtime anomalies and port-defined checks.
353
+ *
354
+ * @note    The default is @p FALSE.
355
+ */
356
+#define CH_DBG_ENABLE_ASSERTS               TRUE
357
+
358
+/**
359
+ * @brief   Debug option, trace buffer.
360
+ * @details If enabled then the context switch circular trace buffer is
361
+ *          activated.
362
+ *
363
+ * @note    The default is @p FALSE.
364
+ */
365
+#define CH_DBG_ENABLE_TRACE                 TRUE
366
+
367
+/**
368
+ * @brief   Debug option, stack checks.
369
+ * @details If enabled then a runtime stack check is performed.
370
+ *
371
+ * @note    The default is @p FALSE.
372
+ * @note    The stack check is performed in a architecture/port dependent way.
373
+ *          It may not be implemented or some ports.
374
+ * @note    The default failure mode is to halt the system with the global
375
+ *          @p panic_msg variable set to @p NULL.
376
+ */
377
+#define CH_DBG_ENABLE_STACK_CHECK           TRUE
378
+
379
+/**
380
+ * @brief   Debug option, stacks initialization.
381
+ * @details If enabled then the threads working area is filled with a byte
382
+ *          value when a thread is created. This can be useful for the
383
+ *          runtime measurement of the used stack.
384
+ *
385
+ * @note    The default is @p FALSE.
386
+ */
387
+#define CH_DBG_FILL_THREADS                 TRUE
388
+
389
+/**
390
+ * @brief   Debug option, threads profiling.
391
+ * @details If enabled then a field is added to the @p thread_t structure that
392
+ *          counts the system ticks occurred while executing the thread.
393
+ *
394
+ * @note    The default is @p FALSE.
395
+ * @note    This debug option is not currently compatible with the
396
+ *          tickless mode.
397
+ */
398
+#define CH_DBG_THREADS_PROFILING            FALSE
399
+
400
+/** @} */
401
+
402
+/*===========================================================================*/
403
+/**
404
+ * @name Kernel hooks
405
+ * @{
406
+ */
407
+/*===========================================================================*/
408
+
409
+/**
410
+ * @brief   Threads descriptor structure extension.
411
+ * @details User fields added to the end of the @p thread_t structure.
412
+ */
413
+#define CH_CFG_THREAD_EXTRA_FIELDS                                          \
414
+  /* Add threads custom fields here.*/
415
+
416
+/**
417
+ * @brief   Threads initialization hook.
418
+ * @details User initialization code added to the @p chThdInit() API.
419
+ *
420
+ * @note    It is invoked from within @p chThdInit() and implicitly from all
421
+ *          the threads creation APIs.
422
+ */
423
+#define CH_CFG_THREAD_INIT_HOOK(tp) {                                       \
424
+  /* Add threads initialization code here.*/                                \
425
+}
426
+
427
+/**
428
+ * @brief   Threads finalization hook.
429
+ * @details User finalization code added to the @p chThdExit() API.
430
+ *
431
+ * @note    It is inserted into lock zone.
432
+ * @note    It is also invoked when the threads simply return in order to
433
+ *          terminate.
434
+ */
435
+#define CH_CFG_THREAD_EXIT_HOOK(tp) {                                       \
436
+  /* Add threads finalization code here.*/                                  \
437
+}
438
+
439
+/**
440
+ * @brief   Context switch hook.
441
+ * @details This hook is invoked just before switching between threads.
442
+ */
443
+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) {                              \
444
+  /* Context switch code here.*/                                            \
445
+}
446
+
447
+/**
448
+ * @brief   Idle thread enter hook.
449
+ * @note    This hook is invoked within a critical zone, no OS functions
450
+ *          should be invoked from here.
451
+ * @note    This macro can be used to activate a power saving mode.
452
+ */
453
+#define CH_CFG_IDLE_ENTER_HOOK() {                                          \
454
+}
455
+
456
+/**
457
+ * @brief   Idle thread leave hook.
458
+ * @note    This hook is invoked within a critical zone, no OS functions
459
+ *          should be invoked from here.
460
+ * @note    This macro can be used to deactivate a power saving mode.
461
+ */
462
+#define CH_CFG_IDLE_LEAVE_HOOK() {                                          \
463
+}
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+
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+/**
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+ * @brief   Idle Loop hook.
467
+ * @details This hook is continuously invoked by the idle thread loop.
468
+ */
469
+#define CH_CFG_IDLE_LOOP_HOOK() {                                           \
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+  /* Idle loop code here.*/                                                 \
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+}
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+
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+/**
474
+ * @brief   System tick event hook.
475
+ * @details This hook is invoked in the system tick handler immediately
476
+ *          after processing the virtual timers queue.
477
+ */
478
+#define CH_CFG_SYSTEM_TICK_HOOK() {                                         \
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+  /* System tick event code here.*/                                         \
480
+}
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+
482
+/**
483
+ * @brief   System halt hook.
484
+ * @details This hook is invoked in case to a system halting error before
485
+ *          the system is halted.
486
+ */
487
+#define CH_CFG_SYSTEM_HALT_HOOK(reason) {                                   \
488
+  /* System halt code here.*/                                               \
489
+}
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+
491
+/** @} */
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+
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+/*===========================================================================*/
494
+/* Port-specific settings (override port settings defaulted in chcore.h).    */
495
+/*===========================================================================*/
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+
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+#endif  /* _CHCONF_H_ */
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+
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+/** @} */

+ 381
- 0
halconf.h View File

@@ -0,0 +1,381 @@
1
+/*
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+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3
+
4
+    Licensed under the Apache License, Version 2.0 (the "License");
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+    you may not use this file except in compliance with the License.
6
+    You may obtain a copy of the License at
7
+
8
+        http://www.apache.org/licenses/LICENSE-2.0
9
+
10
+    Unless required by applicable law or agreed to in writing, software
11
+    distributed under the License is distributed on an "AS IS" BASIS,
12
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+    See the License for the specific language governing permissions and
14
+    limitations under the License.
15
+*/
16
+
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+/**
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+ * @file    templates/halconf.h
19
+ * @brief   HAL configuration header.
20
+ * @details HAL configuration file, this file allows to enable or disable the
21
+ *          various device drivers from your application. You may also use
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+ *          this file in order to override the device drivers default settings.
23
+ *
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+ * @addtogroup HAL_CONF
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+ * @{
26
+ */
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+
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+#ifndef _HALCONF_H_
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+#define _HALCONF_H_
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+
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+#include "mcuconf.h"
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+
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+/**
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+ * @brief   Enables the PAL subsystem.
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+ */
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+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
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+#define HAL_USE_PAL                 TRUE
38
+#endif
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+
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+/**
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+ * @brief   Enables the ADC subsystem.
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+ */
43
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
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+#define HAL_USE_ADC                 FALSE
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+#endif
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+
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+/**
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+ * @brief   Enables the CAN subsystem.
49
+ */
50
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
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+#define HAL_USE_CAN                 FALSE
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+#endif
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+
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+/**
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+ * @brief   Enables the DAC subsystem.
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+ */
57
+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
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+#define HAL_USE_DAC                 FALSE
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+#endif
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+
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+/**
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+ * @brief   Enables the EXT subsystem.
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+ */
64
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
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+#define HAL_USE_EXT                 FALSE
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+#endif
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+
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+/**
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+ * @brief   Enables the GPT subsystem.
70
+ */
71
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
72
+#define HAL_USE_GPT                 FALSE
73
+#endif
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+
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+/**
76
+ * @brief   Enables the I2C subsystem.
77
+ */
78
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
79
+#define HAL_USE_I2C                 FALSE
80
+#endif
81
+
82
+/**
83
+ * @brief   Enables the I2S subsystem.
84
+ */
85
+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
86
+#define HAL_USE_I2S                 FALSE
87
+#endif
88
+
89
+/**
90
+ * @brief   Enables the ICU subsystem.
91
+ */
92
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
93
+#define HAL_USE_ICU                 FALSE
94
+#endif
95
+
96
+/**
97
+ * @brief   Enables the MAC subsystem.
98
+ */
99
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
100
+#define HAL_USE_MAC                 FALSE
101
+#endif
102
+
103
+/**
104
+ * @brief   Enables the MMC_SPI subsystem.
105
+ */
106
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
107
+#define HAL_USE_MMC_SPI             FALSE
108
+#endif
109
+
110
+/**
111
+ * @brief   Enables the PWM subsystem.
112
+ */
113
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
114
+#define HAL_USE_PWM                 FALSE
115
+#endif
116
+
117
+/**
118
+ * @brief   Enables the RTC subsystem.
119
+ */
120
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
121
+#define HAL_USE_RTC                 FALSE
122
+#endif
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+
124
+/**
125
+ * @brief   Enables the SDC subsystem.
126
+ */
127
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
128
+#define HAL_USE_SDC                 FALSE
129
+#endif
130
+
131
+/**
132
+ * @brief   Enables the SERIAL subsystem.