PD Buddy Sink Firmware
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  1. /*
  2. * PD Buddy - USB Power Delivery for everyone
  3. * Copyright (C) 2017-2018 Clayton G. Hobbs <clay@lakeserv.net>
  4. *
  5. * This program is free software: you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation, either version 3 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. /*
  19. ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
  20. Licensed under the Apache License, Version 2.0 (the "License");
  21. you may not use this file except in compliance with the License.
  22. You may obtain a copy of the License at
  23. http://www.apache.org/licenses/LICENSE-2.0
  24. Unless required by applicable law or agreed to in writing, software
  25. distributed under the License is distributed on an "AS IS" BASIS,
  26. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  27. See the License for the specific language governing permissions and
  28. limitations under the License.
  29. */
  30. #ifndef _MCUCONF_H_
  31. #define _MCUCONF_H_
  32. /*
  33. * STM32F0xx drivers configuration.
  34. * The following settings override the default settings present in
  35. * the various device driver implementation headers.
  36. * Note that the settings for each driver only have effect if the whole
  37. * driver is enabled in halconf.h.
  38. *
  39. * IRQ priorities:
  40. * 3...0 Lowest...Highest.
  41. *
  42. * DMA priorities:
  43. * 0...3 Lowest...Highest.
  44. */
  45. #define STM32F0xx_MCUCONF
  46. /*
  47. * HAL driver system settings.
  48. */
  49. #define STM32_NO_INIT FALSE
  50. #define STM32_PVD_ENABLE FALSE
  51. #define STM32_PLS STM32_PLS_LEV0
  52. #define STM32_HSI_ENABLED TRUE
  53. #define STM32_HSI14_ENABLED TRUE
  54. #define STM32_HSI48_ENABLED FALSE
  55. #define STM32_LSI_ENABLED TRUE
  56. #define STM32_HSE_ENABLED FALSE
  57. #define STM32_LSE_ENABLED FALSE
  58. #define STM32_SW STM32_SW_PLL
  59. #define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
  60. #define STM32_PREDIV_VALUE 1
  61. #define STM32_PLLMUL_VALUE 12
  62. #define STM32_HPRE STM32_HPRE_DIV1
  63. #define STM32_PPRE STM32_PPRE_DIV1
  64. #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
  65. #define STM32_MCOPRE STM32_MCOPRE_DIV1
  66. #define STM32_PLLNODIV STM32_PLLNODIV_DIV2
  67. #define STM32_USBSW STM32_USBSW_HSI48
  68. #define STM32_CECSW STM32_CECSW_HSI
  69. #define STM32_I2C1SW STM32_I2C1SW_HSI
  70. #define STM32_USART1SW STM32_USART1SW_PCLK
  71. #define STM32_RTCSEL STM32_RTCSEL_LSI
  72. /*
  73. * ADC driver system settings.
  74. */
  75. #define STM32_ADC_USE_ADC1 FALSE
  76. #define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
  77. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  78. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
  79. #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
  80. /*
  81. * CAN driver system settings.
  82. */
  83. #define STM32_CAN_USE_CAN1 FALSE
  84. #define STM32_CAN_CAN1_IRQ_PRIORITY 3
  85. /*
  86. * DAC driver system settings.
  87. */
  88. #define STM32_DAC_DUAL_MODE FALSE
  89. #define STM32_DAC_USE_DAC1_CH1 TRUE
  90. #define STM32_DAC_USE_DAC1_CH2 TRUE
  91. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
  92. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
  93. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
  94. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
  95. #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  96. #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  97. /*
  98. * EXT driver system settings.
  99. */
  100. #define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
  101. #define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
  102. #define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
  103. #define STM32_EXT_EXTI16_IRQ_PRIORITY 3
  104. #define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
  105. #define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
  106. /*
  107. * GPT driver system settings.
  108. */
  109. #define STM32_GPT_USE_TIM1 FALSE
  110. #define STM32_GPT_USE_TIM2 FALSE
  111. #define STM32_GPT_USE_TIM3 FALSE
  112. #define STM32_GPT_USE_TIM6 FALSE
  113. #define STM32_GPT_USE_TIM14 FALSE
  114. #define STM32_GPT_TIM1_IRQ_PRIORITY 2
  115. #define STM32_GPT_TIM2_IRQ_PRIORITY 2
  116. #define STM32_GPT_TIM3_IRQ_PRIORITY 2
  117. #define STM32_GPT_TIM6_IRQ_PRIORITY 2
  118. #define STM32_GPT_TIM14_IRQ_PRIORITY 2
  119. /*
  120. * I2C driver system settings.
  121. */
  122. #define STM32_I2C_USE_I2C1 FALSE
  123. #define STM32_I2C_USE_I2C2 TRUE
  124. #define STM32_I2C_BUSY_TIMEOUT 50
  125. #define STM32_I2C_I2C1_IRQ_PRIORITY 3
  126. #define STM32_I2C_I2C2_IRQ_PRIORITY 3
  127. #define STM32_I2C_USE_DMA TRUE
  128. #define STM32_I2C_I2C1_DMA_PRIORITY 1
  129. #define STM32_I2C_I2C2_DMA_PRIORITY 1
  130. #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  131. #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  132. #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  133. #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  134. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  135. /*
  136. * I2S driver system settings.
  137. */
  138. #define STM32_I2S_USE_SPI1 FALSE
  139. #define STM32_I2S_USE_SPI2 FALSE
  140. #define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
  141. STM32_I2S_MODE_RX)
  142. #define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
  143. STM32_I2S_MODE_RX)
  144. #define STM32_I2S_SPI1_IRQ_PRIORITY 2
  145. #define STM32_I2S_SPI2_IRQ_PRIORITY 2
  146. #define STM32_I2S_SPI1_DMA_PRIORITY 1
  147. #define STM32_I2S_SPI2_DMA_PRIORITY 1
  148. #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  149. #define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  150. #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  151. #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  152. #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
  153. /*
  154. * I2S driver system settings.
  155. */
  156. #define STM32_I2S_USE_SPI1 FALSE
  157. #define STM32_I2S_USE_SPI2 FALSE
  158. #define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
  159. STM32_I2S_MODE_RX)
  160. #define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
  161. STM32_I2S_MODE_RX)
  162. #define STM32_I2S_SPI1_IRQ_PRIORITY 2
  163. #define STM32_I2S_SPI2_IRQ_PRIORITY 2
  164. #define STM32_I2S_SPI1_DMA_PRIORITY 1
  165. #define STM32_I2S_SPI2_DMA_PRIORITY 1
  166. #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  167. #define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  168. #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  169. #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  170. #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
  171. /*
  172. * ICU driver system settings.
  173. */
  174. #define STM32_ICU_USE_TIM1 FALSE
  175. #define STM32_ICU_USE_TIM2 FALSE
  176. #define STM32_ICU_USE_TIM3 FALSE
  177. #define STM32_ICU_TIM1_IRQ_PRIORITY 3
  178. #define STM32_ICU_TIM2_IRQ_PRIORITY 3
  179. #define STM32_ICU_TIM3_IRQ_PRIORITY 3
  180. /*
  181. * PWM driver system settings.
  182. */
  183. #define STM32_PWM_USE_ADVANCED FALSE
  184. #define STM32_PWM_USE_TIM1 FALSE
  185. #define STM32_PWM_USE_TIM2 FALSE
  186. #define STM32_PWM_USE_TIM3 FALSE
  187. #define STM32_PWM_TIM1_IRQ_PRIORITY 3
  188. #define STM32_PWM_TIM2_IRQ_PRIORITY 3
  189. #define STM32_PWM_TIM3_IRQ_PRIORITY 3
  190. /*
  191. * SERIAL driver system settings.
  192. */
  193. #define STM32_SERIAL_USE_USART1 FALSE
  194. #define STM32_SERIAL_USE_USART2 FALSE
  195. #define STM32_SERIAL_USART1_PRIORITY 3
  196. #define STM32_SERIAL_USART2_PRIORITY 3
  197. /*
  198. * SPI driver system settings.
  199. */
  200. #define STM32_SPI_USE_SPI1 FALSE
  201. #define STM32_SPI_USE_SPI2 FALSE
  202. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  203. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  204. #define STM32_SPI_SPI1_IRQ_PRIORITY 2
  205. #define STM32_SPI_SPI2_IRQ_PRIORITY 2
  206. #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  207. #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  208. #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  209. #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  210. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  211. /*
  212. * ST driver system settings.
  213. */
  214. #define STM32_ST_IRQ_PRIORITY 2
  215. #define STM32_ST_USE_TIMER 2
  216. /*
  217. * UART driver system settings.
  218. */
  219. #define STM32_UART_USE_USART1 FALSE
  220. #define STM32_UART_USE_USART2 FALSE
  221. #define STM32_UART_USART1_IRQ_PRIORITY 3
  222. #define STM32_UART_USART2_IRQ_PRIORITY 3
  223. #define STM32_UART_USART1_DMA_PRIORITY 0
  224. #define STM32_UART_USART2_DMA_PRIORITY 0
  225. #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  226. #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  227. #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  228. #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  229. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  230. /*
  231. * USB driver system settings.
  232. */
  233. #define STM32_USB_USE_USB1 TRUE
  234. #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
  235. #define STM32_USB_USB1_LP_IRQ_PRIORITY 3
  236. /*
  237. * WDG driver system settings.
  238. */
  239. #define STM32_WDG_USE_IWDG FALSE
  240. #endif /* _MCUCONF_H_ */