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pd-buddy-firmware/mcuconf.h

mcuconf.h 10KB
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  1. /*

  2.  * PD Buddy - USB Power Delivery for everyone

  3.  * Copyright (C) 2017 Clayton G. Hobbs <clay@lakeserv.net>

  4.  *

  5.  * This program is free software: you can redistribute it and/or modify

  6.  * it under the terms of the GNU General Public License as published by

  7.  * the Free Software Foundation, either version 3 of the License, or

  8.  * (at your option) any later version.

  9.  *

  10.  * This program is distributed in the hope that it will be useful,

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

  13.  * GNU General Public License for more details.

  14.  *

  15.  * You should have received a copy of the GNU General Public License

  16.  * along with this program.  If not, see <http://www.gnu.org/licenses/>.

  17.  */

  18. 

  19. /*

  20.     ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

  21. 

  22.     Licensed under the Apache License, Version 2.0 (the "License");

  23.     you may not use this file except in compliance with the License.

  24.     You may obtain a copy of the License at

  25. 

  26.         http://www.apache.org/licenses/LICENSE-2.0

  27. 

  28.     Unless required by applicable law or agreed to in writing, software

  29.     distributed under the License is distributed on an "AS IS" BASIS,

  30.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

  31.     See the License for the specific language governing permissions and

  32.     limitations under the License.

  33. */

  34. 

  35. #ifndef _MCUCONF_H_

  36. #define _MCUCONF_H_

  37. 

  38. /*

  39.  * STM32F0xx drivers configuration.

  40.  * The following settings override the default settings present in

  41.  * the various device driver implementation headers.

  42.  * Note that the settings for each driver only have effect if the whole

  43.  * driver is enabled in halconf.h.

  44.  *

  45.  * IRQ priorities:

  46.  * 3...0       Lowest...Highest.

  47.  *

  48.  * DMA priorities:

  49.  * 0...3        Lowest...Highest.

  50.  */

  51. 

  52. #define STM32F0xx_MCUCONF

  53. 

  54. /*

  55.  * HAL driver system settings.

  56.  */

  57. #define STM32_NO_INIT                       FALSE

  58. #define STM32_PVD_ENABLE                    FALSE

  59. #define STM32_PLS                           STM32_PLS_LEV0

  60. #define STM32_HSI_ENABLED                   TRUE

  61. #define STM32_HSI14_ENABLED                 TRUE

  62. #define STM32_HSI48_ENABLED                 FALSE

  63. #define STM32_LSI_ENABLED                   TRUE

  64. #define STM32_HSE_ENABLED                   FALSE

  65. #define STM32_LSE_ENABLED                   FALSE

  66. #define STM32_SW                            STM32_SW_PLL

  67. #define STM32_PLLSRC                        STM32_PLLSRC_HSI_DIV2

  68. #define STM32_PREDIV_VALUE                  1

  69. #define STM32_PLLMUL_VALUE                  12

  70. #define STM32_HPRE                          STM32_HPRE_DIV1

  71. #define STM32_PPRE                          STM32_PPRE_DIV1

  72. #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK

  73. #define STM32_MCOPRE                        STM32_MCOPRE_DIV1

  74. #define STM32_PLLNODIV                      STM32_PLLNODIV_DIV2

  75. #define STM32_USBSW                         STM32_USBSW_HSI48

  76. #define STM32_CECSW                         STM32_CECSW_HSI

  77. #define STM32_I2C1SW                        STM32_I2C1SW_HSI

  78. #define STM32_USART1SW                      STM32_USART1SW_PCLK

  79. #define STM32_RTCSEL                        STM32_RTCSEL_LSI

  80. 

  81. /*

  82.  * ADC driver system settings.

  83.  */

  84. #define STM32_ADC_USE_ADC1                  FALSE

  85. #define STM32_ADC_ADC1_CKMODE               STM32_ADC_CKMODE_ADCCLK

  86. #define STM32_ADC_ADC1_DMA_PRIORITY         2

  87. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2

  88. #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)

  89. 

  90. /*

  91.  * CAN driver system settings.

  92.  */

  93. #define STM32_CAN_USE_CAN1                  FALSE

  94. #define STM32_CAN_CAN1_IRQ_PRIORITY         3

  95. 

  96. /*

  97.  * DAC driver system settings.

  98.  */

  99. #define STM32_DAC_DUAL_MODE                 FALSE

  100. #define STM32_DAC_USE_DAC1_CH1              TRUE

  101. #define STM32_DAC_USE_DAC1_CH2              TRUE

  102. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10

  103. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

  104. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

  105. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

  106. #define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 3)

  107. #define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 4)

  108. 

  109. /*

  110.  * EXT driver system settings.

  111.  */

  112. #define STM32_EXT_EXTI0_1_IRQ_PRIORITY      3

  113. #define STM32_EXT_EXTI2_3_IRQ_PRIORITY      3

  114. #define STM32_EXT_EXTI4_15_IRQ_PRIORITY     3

  115. #define STM32_EXT_EXTI16_IRQ_PRIORITY       3

  116. #define STM32_EXT_EXTI17_20_IRQ_PRIORITY    3

  117. #define STM32_EXT_EXTI21_22_IRQ_PRIORITY    3

  118. 

  119. /*

  120.  * GPT driver system settings.

  121.  */

  122. #define STM32_GPT_USE_TIM1                  FALSE

  123. #define STM32_GPT_USE_TIM2                  FALSE

  124. #define STM32_GPT_USE_TIM3                  FALSE

  125. #define STM32_GPT_USE_TIM6                  FALSE

  126. #define STM32_GPT_USE_TIM14                 FALSE

  127. #define STM32_GPT_TIM1_IRQ_PRIORITY         2

  128. #define STM32_GPT_TIM2_IRQ_PRIORITY         2

  129. #define STM32_GPT_TIM3_IRQ_PRIORITY         2

  130. #define STM32_GPT_TIM6_IRQ_PRIORITY         2

  131. #define STM32_GPT_TIM14_IRQ_PRIORITY        2

  132. 

  133. /*

  134.  * I2C driver system settings.

  135.  */

  136. #define STM32_I2C_USE_I2C1                  FALSE

  137. #define STM32_I2C_USE_I2C2                  TRUE

  138. #define STM32_I2C_BUSY_TIMEOUT              50

  139. #define STM32_I2C_I2C1_IRQ_PRIORITY         3

  140. #define STM32_I2C_I2C2_IRQ_PRIORITY         3

  141. #define STM32_I2C_USE_DMA                   TRUE

  142. #define STM32_I2C_I2C1_DMA_PRIORITY         1

  143. #define STM32_I2C_I2C2_DMA_PRIORITY         1

  144. #define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

  145. #define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

  146. #define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

  147. #define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

  148. #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")

  149. 

  150. /*

  151.  * I2S driver system settings.

  152.  */

  153. #define STM32_I2S_USE_SPI1                  FALSE

  154. #define STM32_I2S_USE_SPI2                  FALSE

  155. #define STM32_I2S_SPI1_MODE                 (STM32_I2S_MODE_MASTER |        \

  156.                                              STM32_I2S_MODE_RX)

  157. #define STM32_I2S_SPI2_MODE                 (STM32_I2S_MODE_MASTER |        \

  158.                                              STM32_I2S_MODE_RX)

  159. #define STM32_I2S_SPI1_IRQ_PRIORITY         2

  160. #define STM32_I2S_SPI2_IRQ_PRIORITY         2

  161. #define STM32_I2S_SPI1_DMA_PRIORITY         1

  162. #define STM32_I2S_SPI2_DMA_PRIORITY         1

  163. #define STM32_I2S_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

  164. #define STM32_I2S_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

  165. #define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

  166. #define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

  167. #define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")

  168. 

  169. /*

  170.  * I2S driver system settings.

  171.  */

  172. #define STM32_I2S_USE_SPI1                  FALSE

  173. #define STM32_I2S_USE_SPI2                  FALSE

  174. #define STM32_I2S_SPI1_MODE                 (STM32_I2S_MODE_MASTER |        \

  175.                                              STM32_I2S_MODE_RX)

  176. #define STM32_I2S_SPI2_MODE                 (STM32_I2S_MODE_MASTER |        \

  177.                                              STM32_I2S_MODE_RX)

  178. #define STM32_I2S_SPI1_IRQ_PRIORITY         2

  179. #define STM32_I2S_SPI2_IRQ_PRIORITY         2

  180. #define STM32_I2S_SPI1_DMA_PRIORITY         1

  181. #define STM32_I2S_SPI2_DMA_PRIORITY         1

  182. #define STM32_I2S_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

  183. #define STM32_I2S_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

  184. #define STM32_I2S_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

  185. #define STM32_I2S_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

  186. #define STM32_I2S_DMA_ERROR_HOOK(i2sp)      osalSysHalt("DMA failure")

  187. 

  188. /*

  189.  * ICU driver system settings.

  190.  */

  191. #define STM32_ICU_USE_TIM1                  FALSE

  192. #define STM32_ICU_USE_TIM2                  FALSE

  193. #define STM32_ICU_USE_TIM3                  FALSE

  194. #define STM32_ICU_TIM1_IRQ_PRIORITY         3

  195. #define STM32_ICU_TIM2_IRQ_PRIORITY         3

  196. #define STM32_ICU_TIM3_IRQ_PRIORITY         3

  197. 

  198. /*

  199.  * PWM driver system settings.

  200.  */

  201. #define STM32_PWM_USE_ADVANCED              FALSE

  202. #define STM32_PWM_USE_TIM1                  FALSE

  203. #define STM32_PWM_USE_TIM2                  FALSE

  204. #define STM32_PWM_USE_TIM3                  FALSE

  205. #define STM32_PWM_TIM1_IRQ_PRIORITY         3

  206. #define STM32_PWM_TIM2_IRQ_PRIORITY         3

  207. #define STM32_PWM_TIM3_IRQ_PRIORITY         3

  208. 

  209. /*

  210.  * SERIAL driver system settings.

  211.  */

  212. #define STM32_SERIAL_USE_USART1             FALSE

  213. #define STM32_SERIAL_USE_USART2             FALSE

  214. #define STM32_SERIAL_USART1_PRIORITY        3

  215. #define STM32_SERIAL_USART2_PRIORITY        3

  216. 

  217. /*

  218.  * SPI driver system settings.

  219.  */

  220. #define STM32_SPI_USE_SPI1                  FALSE

  221. #define STM32_SPI_USE_SPI2                  FALSE

  222. #define STM32_SPI_SPI1_DMA_PRIORITY         1

  223. #define STM32_SPI_SPI2_DMA_PRIORITY         1

  224. #define STM32_SPI_SPI1_IRQ_PRIORITY         2

  225. #define STM32_SPI_SPI2_IRQ_PRIORITY         2

  226. #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

  227. #define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

  228. #define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

  229. #define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

  230. #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")

  231. 

  232. /*

  233.  * ST driver system settings.

  234.  */

  235. #define STM32_ST_IRQ_PRIORITY               2

  236. #define STM32_ST_USE_TIMER                  2

  237. 

  238. /*

  239.  * UART driver system settings.

  240.  */

  241. #define STM32_UART_USE_USART1               FALSE

  242. #define STM32_UART_USE_USART2               FALSE

  243. #define STM32_UART_USART1_IRQ_PRIORITY      3

  244. #define STM32_UART_USART2_IRQ_PRIORITY      3

  245. #define STM32_UART_USART1_DMA_PRIORITY      0

  246. #define STM32_UART_USART2_DMA_PRIORITY      0

  247. #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

  248. #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

  249. #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

  250. #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)

  251. #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")

  252. 

  253. /*

  254.  * USB driver system settings.

  255.  */

  256. #define STM32_USB_USE_USB1                  TRUE

  257. #define STM32_USB_LOW_POWER_ON_SUSPEND      FALSE

  258. #define STM32_USB_USB1_LP_IRQ_PRIORITY      3

  259. 

  260. /*

  261.  * WDG driver system settings.

  262.  */

  263. #define STM32_WDG_USE_IWDG                  FALSE

  264. 

  265. #endif /* _MCUCONF_H_ */